16 Bit DLL Multiplier Using Low Power Pulse Generator

  Piyush Chimote,  Dr. Manish Sharma

A highly faithful, high-speed and power efficient frequency multiplier is planned for a clock generator based on delay-locked loop to produce a multiplied clock with a max frequency range. The planned edge combiner attains a highly reliable and high-speed operation using flap canceller and hierarchical structure. In accumulation, by relating the logical work to the control logic design of multiplication-ratio and pulse generator, the planned frequency multiplier reduces the lag difference among negative and positive-edge propagation paths that cause a deterministic jitter. At last, a mathematical analysis is implemented to compare and examine the act of the planned frequency multiplier with that of previous frequency multipliers. The 0.18-μm CMOS process technology is customized to construct the desired frequency multiplier which is having the multiplication ratios of 1, 2, 4, 8, and 16 and an output range between 90 MHz to 3.2 GHz.

Keywords- Jitter, Delay-Locked Loop, flap canceller, multiplication ratio

Unique Identification Number - IJEDR1803110
Page Number(s) - 663-666
Pubished in - Volume 6 | Issue 3 | September 2018
DOI (Digital Object Identifier) -   
Publisher - IJEDR (ISSN - 2321-9939)

  Piyush Chimote,  Dr. Manish Sharma,   "16 Bit DLL Multiplier Using Low Power Pulse Generator", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.6, Issue 3, pp.663-666, September 2018, Available at :http://www.ijedr.org/papers/IJEDR1803110.pdf