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Paper Details
Paper Title
Design and Analysis of Vedic Multiplier by Using Modified Full Adders
Authors
Manpreet Kaur, Er. Amandeep Kaur
Abstract
In digital circuits multiplier plays a very important role. These are the main important blocks in many applications like digital signal processing, microprocessor and microcomputers. The time that required doing calculation in multiplier is reduced by using Vedic multipliers. Vedic Mathematics is the fastest and low power multiplier. Vedic Mathematics have sixteen sutras but “Urdhva Tiryagbhyam” is mainly used .In this paper 16 bit Vedic multiplier is designed by using modified full adders which has used less number of slices and delay is reduced when compared to existing techniques of Vedic Multiplier. In this paper Vedic Multiplier using modified full adder 2 has better performance as compare to other modified full adders. Simulation and synthesis are carried on XILINX ISE 14.4 software.
Keywords- Vedic Multiplier, Full Adder using Multiplexer, Ripple Carry Adder, VLSI.
Publication Details
Unique Identification Number - IJEDR1802149Page Number(s) - 807-811Pubished in - Volume 6 | Issue 2 | June 2018DOI (Digital Object Identifier) - Publisher - IJEDR (ISSN - 2321-9939)
Cite this Article
Manpreet Kaur, Er. Amandeep Kaur, "Design and Analysis of Vedic Multiplier by Using Modified Full Adders", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.6, Issue 2, pp.807-811, June 2018, Available at :http://www.ijedr.org/papers/IJEDR1802149.pdf
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