Design of Ultra Low Voltage SRAM in Corporating Novel Capacitor Based Boosted Word Line

  Md Atique Hassan ,  Kamil Hasan,  Nitin Sehgal

Design techniques to realize input/output circuits used to access six-transistor- 6T Static Random Access Memory- SRAM cell based memory array in ultra low voltage applications. The main thrust of this work is to optimize access speed and power consumption- static & switching, of SRAM based memory circuit, especially of large width memories in ultra low voltage applications. A novel design for capacitor based boosting technique is introduced in the access as well as input/output circuits. Capacitor based boosting technique compensates for high capacitance of lengthy access routes, encountered in large capacity memories, and inadequate gate drive owing to supply power scaling. Other low voltage techniques, such as pre-decoding, are realized in conjunction with boosting capacitor technique to overcome the SRAM cell’s variations and thus achieve fast, low power SRAM operation .The capacitor based boosting technique also reduces chip area occupancy by doing away with large inverter circuits required to drive large capacitance access paths.

Keywords- path ,low power ,multi stage decoding ,voltage boosting

Unique Identification Number - IJEDR1602322
Page Number(s) - 1840-1842
Pubished in - Volume 4 | Issue 2 | June 2016
DOI (Digital Object Identifier) -   
Publisher - IJEDR (ISSN - 2321-9939)

  Md Atique Hassan ,  Kamil Hasan,  Nitin Sehgal,   "Design of Ultra Low Voltage SRAM in Corporating Novel Capacitor Based Boosted Word Line", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.4, Issue 2, pp.1840-1842, June 2016, Available at :http://www.ijedr.org/papers/IJEDR1602322.pdf