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Paper Details
Paper Title
Edge Detection in VHDL
Authors
  Mayur Rathod
Abstract
Edge is a basic feature of an image. edge is a collection of the pixels it refers to the part where the brightness of the image local area changes significantly. Real time edge detection is required in many embedded system where execution speed is critical. The VHDL is an appropriate Hardware Description Language (HDL) for providing hardware models of practical image processing algorithms. This paper present study on various edge detectors. Introduction and Comparison between different edge detection algorithms is presented. In this project my Aim is to implement edge detection algorithm on FPGA. The FPGA technology has the advantage of high-performance for digital image processing and low cost. The FPGA provides the necessary hardware for image processing algorithms with flexibility to support edge detection algorithm. HDL Coder is used for MATLAB to vhdl conversion. Simulation result and also edge detected result for sobel and prewitt algorithm using HDL Coder and hand code is presented..
Keywords- Gradient Operator, Edge detection, FPGA, Matlab,HDL coder
Publication Details
Unique Identification Number - IJEDR1401196Page Number(s) - 1095-1099Pubished in - Volume 2 | Issue 1 | March 2014DOI (Digital Object Identifier) -    Publisher - IJEDR (ISSN - 2321-9939)
Cite this Article
  Mayur Rathod,   "Edge Detection in VHDL", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.2, Issue 1, pp.1095-1099, March 2014, Available at :http://www.ijedr.org/papers/IJEDR1401196.pdf
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