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Paper Details
Paper Title
Design of low power gating technique in NAND type CAM cell architecture
Authors
  M. POORANI SWASTHIKA,  G. VIJAYAKUMAR,  R. SUBRAMANIAN
Abstract
Content addressable memory (CAM) is special type of flash memory is used to attain a high speed search function in a single clock cycle throughput making them faster than other hardware- and software-based search system .Binary CAM has a parallel active circuitry which consumes more power to its operation without scarifying its speed and memory .This paper deals with a parity based CAM operation to increase the performance in comparison part of the traditional CAM and NOR type cell is used in CAM architecture The proposed work includes the implementation of NAND/XNOR type CAM cell instead of its NOR type CAM cell which overcomes the limitation of the previously used type cell and obtain the less silicon area by minimizing the number of transistor in each cell. The power gated technique is used in these type of cell to optimize the power in comparison part by automatically turn off the power supply when the respected block is not in enable.
Keywords- Gated power, CMOS, content addressable memory (CAM), NAND-type CAM, searchline
Publication Details
Unique Identification Number - IJEDR1401099Page Number(s) - 552-557Pubished in - Volume 2 | Issue 1 | March 2014DOI (Digital Object Identifier) -    Publisher - IJEDR (ISSN - 2321-9939)
Cite this Article
  M. POORANI SWASTHIKA,  G. VIJAYAKUMAR,  R. SUBRAMANIAN,   "Design of low power gating technique in NAND type CAM cell architecture", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.2, Issue 1, pp.552-557, March 2014, Available at :http://www.ijedr.org/papers/IJEDR1401099.pdf
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