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Paper Details
Paper Title
Design and simulation of AES algorithm- Encryption using VHDL
Authors
  Mital Maheta
Abstract
The Cryptographic Algorithm is most widely used throughout the world for protecting information. Cryptography is the art of secret writing, followed by the guarantee to authenticate data and important messages and protect the systems from valid attacks. It comprises of encryption and decryption process each associated with a key which is supposed to be kept secret. We have implement RC6 Algorithm. This is considered as a secured and elegant choice for AES due to its simplicity, security, performance and efficiency. RC6 supports 32 bit and 64 bit processing. An eight step algorithm is used to encipher the 64 bit plain text block. The encrypted data is then decrypted by performing the reverse algorithm on the same. This paper introduces encryption of RC6 using Xilinx 8.1i.
Keywords- AES Algorithm, RC6, Encryption, Cryptography, Cipher text.
Publication Details
Unique Identification Number - IJEDR1401072Page Number(s) - 415-418Pubished in - Volume 2 | Issue 1 | March 2014DOI (Digital Object Identifier) -    Publisher - IJEDR (ISSN - 2321-9939)
Cite this Article
  Mital Maheta,   "Design and simulation of AES algorithm- Encryption using VHDL", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.2, Issue 1, pp.415-418, March 2014, Available at :http://www.ijedr.org/papers/IJEDR1401072.pdf
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