Design, Implementation and Analysis of Error Tolerant Adder in CMOS 180nm Technology

  Kusumitha M C,  Shashidhara K S,  Parameshwara M C

The main objective of this work is to design, implement and analyze the error tolerant adder (ETA) for DSP applications. This paper aims at designing ETA using low power and energy efficient one-bit full adders. Further we analyze ETA using state of the art one-bit full adders. All the ETA under consideration are designed by using CMOS 180nm technology. The design metrics such as power, delay, PDP and area in terms of transistor count are extracted under common Process-Voltage-Temperature (PVT) conditions. These design metrics are extracted for inputs signal frequency of 200MHz supply voltage of 1.8V and temperature of. All simulations are carried out using Cadence Spectre Simulator using BSIM Version 3 MOSFET models.

Keywords- Adder, Delay, Power, PDP, ETA

Unique Identification Number - IJEDR1903006
Page Number(s) - 23-27
Pubished in - Volume 7 | Issue 3 | July 2019
DOI (Digital Object Identifier) -   
Publisher - IJEDR (ISSN - 2321-9939)

  Kusumitha M C,  Shashidhara K S,  Parameshwara M C,   "Design, Implementation and Analysis of Error Tolerant Adder in CMOS 180nm Technology", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.7, Issue 3, pp.23-27, July 2019, Available at :http://www.ijedr.org/papers/IJEDR1903006.pdf