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INTERNATIONAL JOURNAL OF ENGINEERING DEVELOPMENT AND RESEARCH
(International Peer Reviewed,Refereed, Indexed, Citation Open Access Journal)
ISSN: 2321-9939 | ESTD Year: 2013

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Paper Title
Performance Comparison of 64-Bit Adders
Authors
  Kishore Prabhala,  Haritha Dasari,  Thrinadh Komatipalli

Abstract
The objective of this paper is to analyze and optimization of adders. Addition is essential operation in any digital, analog and control systems. Adders are part of not only arithmetic logic unit in computers but used in some other kind of processors too, where they are used to calculate addresses, table in dices , and similar operations for that we have to reduce the area. This paper mainly concentrated on the optimization of the area. As number of bits increase to add, the area would be increased to calculate the carry from each section. In this paper, we implemented the adders using mentor graphics tool. Simulation have done by Questa_sim and synthesis by Leonardo spectrum in 135nm technology.

Keywords- Questa_sim , Leonardo spectrum , mentor graphics, optimization, synthesis
Publication Details
Unique Identification Number - IJEDR1802114
Page Number(s) - 626-628
Pubished in - Volume 6 | Issue 2 | June 2018
DOI (Digital Object Identifier) -   
Publisher - IJEDR (ISSN - 2321-9939)
Cite this Article
  Kishore Prabhala,  Haritha Dasari,  Thrinadh Komatipalli,   "Performance Comparison of 64-Bit Adders", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.6, Issue 2, pp.626-628, June 2018, Available at :http://www.ijedr.org/papers/IJEDR1802114.pdf
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