High Performance Cache Architecture Using Victim Cache

  Suyog S. Kandalkar,  Yogesh S. Watile

A CPU is consist of various types of memory. Microprocessor is the first and the leading component of the CPU. With the increasing speed of modern microprocessors, the operating speed of different memories becomes more critical to the system performance. The increasing speed gap between the processors and memories can be matched or adjusted with the help of cache memory. Cache memory are on-chip memory element used to store data. Cache memory is used to increase data transfer rate. The performance of a cache is calculated by its ability of differentiate and maintaining the data that the program will need in near future and unwanted data will be discarded. This can be understood through replacement policy of the cache controller. A cache controller is used for tracking generated miss rate in cache memory. While using direct mapping technique in cache, there is a fixed cache location for any given block. But due to that two different blocks can map into the same line and the hit ratio will be low. With fully associative mapping, there is flexibility to replace block when a new block read into cache. This review paper proposed the technique this technique is very useful to reduce the miss rate in cache memory. In the proposed technique the direct mapped cache is added with a small associative cache known as victim cache. A line removed from the direct mapped is temporarily store in the victim cache

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Unique Identification Number - IJEDR1703068
Page Number(s) - 457-465
Pubished in - Volume 5 | Issue 3 | July 2017
DOI (Digital Object Identifier) -   
Publisher - IJEDR (ISSN - 2321-9939)

  Suyog S. Kandalkar,  Yogesh S. Watile,   "High Performance Cache Architecture Using Victim Cache", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.5, Issue 3, pp.457-465, July 2017, Available at :http://www.ijedr.org/papers/IJEDR1703068.pdf