A Low Power Design Of Floating Point Multiply Add Unit

  Insha Ishteyaq,  Kantesh Kumar Gaurav,  Heena Gupta

Signal Processing and Image Processing applications require floating point operations in digital circuit design. In order to increase the accuracy of the results the floating point operations are preferred in almost all digital design applications. Various arithmetic operations use floating point calculation and can be used for implementation of various computational and logic unit operations. In the proposed work a fused multiply- addition unit is proposed which utilizes the common addition block for both addition and multiplication operations. The floating point number is first converted into the IEEE 754 format and then the calculation for both addition and multiplication is performed. The significand is extracted from the number and the calculations are performed on the basis of the exponent difference between the numbers. In the proposed approach a parallel architecture is designed which first extracts the significand and exponent value in the first unit and multiplication-addition operations on the second block. The final output is carried out on the third block where normalization and zero detector operations are performed. The proposed approach is then compared with the basic approach and shows improvement in power consumption and maximum combinational path delay. Results shows that the delay is decreased by approx. 17% and power is decreased by approx. 77%.

Keywords- FPU, FMA, Floating-point arithmetic

Unique Identification Number - IJEDR1703037
Page Number(s) - 243-247
Pubished in - Volume 5 | Issue 3 | July 2017
DOI (Digital Object Identifier) -   
Publisher - IJEDR (ISSN - 2321-9939)

  Insha Ishteyaq,  Kantesh Kumar Gaurav,  Heena Gupta,   "A Low Power Design Of Floating Point Multiply Add Unit", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.5, Issue 3, pp.243-247, July 2017, Available at :http://www.ijedr.org/papers/IJEDR1703037.pdf