An Efficient Approach for High Speed Circular Convolution Using 4 Bit Urdhva Triyakbhayam Sutra Based Vedic Multiplier

  Poonam Vachak,  Vineeta Saxena Nigam

Multipliers and dividers are the basic blocks in convolution and de-convolution fabrication, Multipliers and Dividers consumes much of the time for computation, This thesis presents a direct method of computing circular convolution. This approach is simple and easy to implement because of the similarity to computing the multiplication of two numbers. The unique factor of the proposed method is the implementation of multiplier and divider architecture using Ancient Indian Vedic Mathematics sutras Urdhvatriyagbhayam Algorithm. The result shows that the implementation of circular convolution using Vedic mathematics is more efficient than the conventional method in terms of area, speed and delay compared to their implementation using conventional multiplier & divider architectures. In this thesis I have proposed 4bit multiplier using Urdhvatriyagbhayam Sutra, The coding is done in VHDL Software. Simulation and Synthesis are performed using Xilinx ISE design suit 14.2,simulated results for proposed 4x4 bit Vedic convolution circuit shows a reduction in delay of 88% than the conventional method and 41% than the OLA method.

Keywords- vhdl, KSA, Prefix adder, VM, multiplier, adder

Unique Identification Number - IJEDR1703036
Page Number(s) - 239-242
Pubished in - Volume 5 | Issue 3 | July 2017
DOI (Digital Object Identifier) -   
Publisher - IJEDR (ISSN - 2321-9939)

  Poonam Vachak,  Vineeta Saxena Nigam,   "An Efficient Approach for High Speed Circular Convolution Using 4 Bit Urdhva Triyakbhayam Sutra Based Vedic Multiplier", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.5, Issue 3, pp.239-242, July 2017, Available at :http://www.ijedr.org/papers/IJEDR1703036.pdf