FPGA Based Vedic Multiplier

  Mayuri Parag Joshi,  K Nirmalakumari,  Deepali C Shimpi

FIR filters, Microprocessors, DSP and communication application Multipliers are used. To carry higher order multiplication number of adders and compressor required are more to carry out partial product addition. As the need of high speed processor are increasing the need of low power high speed multiplier is also increasing. In this paper, a high performance, high throughput and area efficient architecture of a multiplier for the Field Programmable Gate Array (FPGAs) is proposed. The multiplier is design using vertical and crosswise structure of ancient Indian Vedic multiplier. As per the proposed architecture, for two 4-bit numbers; the multiplier and multiplicand, each are grouped as 2-bit numbers so that it decomposes into 2×2 multiplication modules. The coding is done in VHDL and the FPGA synthesis is done using Xilinx

Keywords- FPGA, Multiplier, Vedic Mathematics

Unique Identification Number - IJEDR1702175
Page Number(s) - 1033-1037
Pubished in - Volume 5 | Issue 2 | May 2017
DOI (Digital Object Identifier) -   
Publisher - IJEDR (ISSN - 2321-9939)

  Mayuri Parag Joshi,  K Nirmalakumari,  Deepali C Shimpi,   "FPGA Based Vedic Multiplier", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.5, Issue 2, pp.1033-1037, May 2017, Available at :http://www.ijedr.org/papers/IJEDR1702175.pdf