FPGA Implementation and Evaluation of lightweight block cipher - BORON

  Tadashi Okabe

This article presents the first hardware implementations of the BORON lightweight block cipher on general purpose field programmable gate arrays (FPGAs) using hardware description language. Herein, we evaluate several architectures for compatibility with the lightweight block cipher algorithm and report on both the first FPGA implementation results along with a comparison with standard lightweight block cipher algorithms. Of particular note, we confirm that BORON provides an excellent hardware performance algorithm for a lightweight block cipher in terms of high performance per unit area and power consumption.

Keywords- FPGA, BORON, Lightweight block cipher, Hardware implementation, CPS, Embedded system.

Unique Identification Number - IJEDR1701033
Page Number(s) - 207-216
Pubished in - Volume 5 | Issue 1 | February 2017
DOI (Digital Object Identifier) -   
Publisher - IJEDR (ISSN - 2321-9939)

  Tadashi Okabe,   "FPGA Implementation and Evaluation of lightweight block cipher - BORON", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.5, Issue 1, pp.207-216, February 2017, Available at :http://www.ijedr.org/papers/IJEDR1701033.pdf