ASIC Implementation of DDR SDRAM Memory Controller

  Ramagiri.Ramya,  Naganaik

A Dedicated Memory Controller is of prime importance in applications that do not contain microprocessors (high-end applications). The Memory Controller provides command signals for memory refresh, read and write operation and initialization of SDRAM. Our work will focus on ASIC Design methodology of Double Data Rate (DDR) SDRAM Controller that is located between the DDR SDRAM and Bus Master. The Controller simplifies the SDRAM command interface to standard system read/write interface and also optimizes the access time of read/write cycle.

Keywords- DDR SDRAM Controller, Read/Write Data path, Cadence RTL Compiler

Unique Identification Number - IJEDR1604008
Page Number(s) - 49-54
Pubished in - Volume 4 | Issue 4 | October 2016
DOI (Digital Object Identifier) -   
Publisher - IJEDR (ISSN - 2321-9939)

  Ramagiri.Ramya,  Naganaik,   "ASIC Implementation of DDR SDRAM Memory Controller", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.4, Issue 4, pp.49-54, October 2016, Available at :http://www.ijedr.org/papers/IJEDR1604008.pdf