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Paper Details
Paper Title
Error Free Iterative Mitchell Algorithm Based Multiplier for Image Filters
Authors
Jeevana B, S Sridevi
Abstract
In digital image processing applications the quality of image depend on the Multipliers. Existing multipliers introduce errors in the output which will require more time, hence error free high speed multipliers has to be designed to overcome this problem. This paper presents a FPGA based iterative Mitchell Algorithm based multiplier for image filters by introducing error correction term in Karastuba-Ofman multiplier (KOM) architectures for image filters. The proposed multiplier is synthesized using Spartan 6 FPGA Family Device XC6SLX45-CSG324. Iterative Mitchell algorithm based multiplier improves the performance parameters such as area utilization, error, speed are better in the case of proposed architecture compared to existing architectures.
Keywords- FPGA, Mitchell log multiplier, Karastuba-Ofman multiplier, PSNR. -.
Publication Details
Unique Identification Number - IJEDR1502189Page Number(s) - 1091-1097Pubished in - Volume 3 | Issue 2 | May 2015DOI (Digital Object Identifier) - Publisher - IJEDR (ISSN - 2321-9939)
Cite this Article
Jeevana B, S Sridevi, "Error Free Iterative Mitchell Algorithm Based Multiplier for Image Filters", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.3, Issue 2, pp.1091-1097, May 2015, Available at :http://www.ijedr.org/papers/IJEDR1502189.pdf
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