Implementation of Parallel Multiplier using Advanced Modified Booth Encoding Algorithm

  Manthan J. Trivedi,  Vimal H. Nayak,  Mohmmed G. Vayada

This research paper represents the implementation of Advanced Modified Booth Encoding (AMBE) parallel Multiplier. The already existed Booth and Baugh Wooly Multipliers are used for only signed numbers, while array multipliers uses only for unsigned numbers. Modern Computer system needs a very high speed parallel multiplier which is used for signed and unsigned numbers. This multiplier is obtained by extending a sign bit from Modified Booth Encoder and generates an additional partial product; the proposed multiplier can be used for both signed and unsigned bits. The Carry Save Adder tree (CSA) and Carry Look Ahead Adder (CLA) are used to add all partial products and generates the final product. This multiplier uses for both signed and unsigned numbers so total chip area reduces and power reduces as well. The Advanced Modified Booth Encoding parallel multiplier for 8 x 8 bits signed-unsigned and 64 x 64 bits signed unsigned multiplier is simulated using Verilog-HDL language in Xilinx 13.2ISE simulator and implements on Spartan 3E starter board.

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Unique Identification Number - IJEDR1502112
Page Number(s) - 623-628
Pubished in - Volume 3 | Issue 2 | May 2015
DOI (Digital Object Identifier) -   
Publisher - IJEDR (ISSN - 2321-9939)

  Manthan J. Trivedi,  Vimal H. Nayak,  Mohmmed G. Vayada,   "Implementation of Parallel Multiplier using Advanced Modified Booth Encoding Algorithm", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.3, Issue 2, pp.623-628, May 2015, Available at :http://www.ijedr.org/papers/IJEDR1502112.pdf