Design and Verification of a 16-bit RISC Processor using Universal Verification Methodology (UVM)

  Ajit Shridhar Gangad,  Prof.C.Prayline Rajabai

This paper presents Design of a 16-Bit RISC Processor supporting Arithmetic ,Logical, Data transfer, Branch instructions such as ADD,MUL ,SUB,AND,OR,EXOR,EXNOR ,RD ,WR,BR,BRZ,NOT,NOP. RISC Processor supporting High Speed ,Low Area ,Low Power Uniform Carry Select Adder (UCSLA), High Speed 16-bit Hybrid Wallace Tree Multiplier .The Design is synthesized with 45nm library .Physical Design flow is performed with Cadence SoC Encounter. Verification environment is prepared by using Universal verification methodology(UVM) is most widely used methodology by verification industry word wide . Verification environment created in UVM which is reusable, efficient and well structured. The 16-bit RISC processor is a Design under test (DUT).The environment created in UVM is completely wrap a DUT. Assertion coverage is found to be 100% , Code Coverage consists of statement, Branch, Toggle, Expression coverage which is found to be 98.30%.Functional Coverage is obtained by writing cover-groups is found to be 99.87%.Overall coverage found to be 99.39%.

Keywords- System Verilog ,DUT, UVM,Functional Coverage,Assertion Based Verification ,RISC.

Unique Identification Number - IJEDR1502072
Page Number(s) - 382-393
Pubished in - Volume 3 | Issue 2 | May 2015
DOI (Digital Object Identifier) -   
Publisher - IJEDR (ISSN - 2321-9939)

  Ajit Shridhar Gangad,  Prof.C.Prayline Rajabai,   "Design and Verification of a 16-bit RISC Processor using Universal Verification Methodology (UVM)", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.3, Issue 2, pp.382-393, May 2015, Available at :http://www.ijedr.org/papers/IJEDR1502072.pdf