Design and Implementation of 16 bit Floating Point Processor for FFT applications

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Paper Details

Paper Title

Design and Implementation of 16 bit Floating Point Processor for FFT applications

Authors

Deepak Dave, Aarti Bakshi

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Abstract

Floating point is considered to be an important format in which data is represented in fraction values. Floating Point calculation can be a daunting task for any processor because of the amount of resources and memory it takes for calculation. In this paper, we have presented and implemented a floating point architecture for application in FFT.

Keywords- Butterfly; Field Programmable Gate Array (FPGA); Verilog HDL; 1024-point FFT

Publication Details

Unique Identification Number - IJEDR1501013
Page Number(s) - 59-64
Pubished in - Volume 3 | Issue 1 | Jan 2015
DOI (Digital Object Identifier) -
Publisher - IJEDR (ISSN - 2321-9939)

Cite this Article

Deepak Dave, Aarti Bakshi, "Design and Implementation of 16 bit Floating Point Processor for FFT applications", International Journal of Engineering Development and Research (IJEDR), ISSN:2321-9939, Volume.3, Issue 1, pp.59-64, Jan 2015, Available at :http://www.ijedr.org/papers/IJEDR1501013.pdf

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